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Lattice Semiconductor
Table 5-1. Test Application Related Registers
Application Support
Address
0x0802c, 0x0802d
0x0802e, 0x0802f
0x08030, 0x08031
0x08032 - 0x0FFFF
Register Description
TX VLAN tagged Frame CouNTer Register (L,H)
TX BAD FCS Frame CouNTer Register (L,H)
TX Jumbo Frame CouNTer Register (L,H)
UNUSED
Mnemonic
TXVFCNT
TXBFCCNT
TXJFCNT
Type
RO/COR
RO/COR
RO/COR
Register Descriptions
Version/Identification (RO)
Mnemonic: VERID
POR Value = A2H
Name
Version_ID [7:0]
Range
7:0
Description
Version ID : Echoes back the version and ID of the application (A2H).
Test Control Register (R/W)
Mnemonic: TSTCNTL
POR Value = 00H
Name
Rsvd
pkt_loop_clksel
reset_phy_n
loop back enable
destination/source
address swap
Range
7:4
3
2
1
0
Description
Reserved
Packet Loop Clock Select : When this bit is set High, sys_clk is tied to
rx_clk. When the bit is Low sys_clk is sourced from an external IO pin.
Reset PHY : When this bit is set High, the phy_reset_n pin is de-asserted
(High). When this bit is Low the phy_reset_n pin is asserted (Low). This pin
can be used to reset an External PHY device.
Loop back Enable : When this bit is set High the client side loop back is
enabled. When the bit is Low the Loop back is disabled.
Swap Destination and Source Addresses: When this bit is set High the
Ethernet Destination and source addresses are swapped . When the bit is
Low there is no address swapping.
Test Control Register 2 (R/W)
Mnemonic: TSTCNTL 2
POR Value = 00H
Name
testcontrol[7:0]
Range
7:0
Reserved.
Description
IPUG51_03.0, December 2010
52
Tri-Speed Ethernet MAC User’s Guide
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